`timescale 1ns/1ns
module stage1tb ();
	
	reg			clk;
	reg			rst;
	reg	[7:0]	indata;
	reg			invalid;
	wire	[7:0] outdata;
	wire			outvalid;
	wire			out_msg_end;
	
	stage1 stage1_im(
		.valid_0_1(invalid),
		.data_0_1(indata),
		.valid_1_2(outvalid),
		.data_1_2(outdata),
		.msg_end_1_2(out_msg_end),
	
		.clk(clk),
		.rst(rst)	//P RST
		);
	
	initial 
	begin
		clk		=	0;
		rst		=	1;
		indata	=	8'b0;
		invalid	=	0;
		#12	rst	=	0;
		
		#10	indata	=	8'b00000001;
				invalid	=	1;
		#20	invalid	=	0;
		
		#10	indata	=	8'b00000010;
				invalid	=	1;
		#20	invalid	=	0;
		
		#10	indata	=	8'b00001111;
				invalid	=	1;
		
		
		
	end
	
	always #10	clk	=	~clk;
		
		
		
endmodule